Dick Cappels' project pages
Minimum Mass Waveform Capture

The low pass filter for the PWM chip needs to be pretty closely matched to the settling times allowed for in the firmware. Before conversion starts, the PWM converter needs to be able to settle to within 1 least significant bit of its final value so that it will not continue to chance more than 1 bit as the waveform is captured. The settling time after changing the PWM output must similarly be allowed to settle so that the PWM voltage does not change during the time it takes to test the 100 timed samples. Since the waveform is being digitized, there will be a quantization effect as long as there is any noise at all in the system, and PWM ripple and settling times is are noise sources. The greater the ripple on the PWM output, the more likely that the measurement will err from its assumed true value during any given sample. The settling time and ripple values are difficult to set because they involve tradeoffs between speed and noise on the output. The longer it takes to make a measurement, the less noisy the output looks for many waveforms.

The 160k and 39k resistors form a 5:1 voltage divider.
The objective of modeling the low pass filter is to allow
determination of the settling time and ripple on the filter.

A simplifying assumptions in modeling the output filter is to assume that the output resistance of the PWM signal from the microcontroller is negligible. Judging from the AT90S2313 data sheet,. when operating at 5 volts, the out put resistance is around 28 Ohms, so its safe to say its negligible compared to the 160k Ohm resistor in series with it. In the simplified model the equivalent series resistance is equal the the parallel combination of the 160k and 39k resistors and the driving signal source is modeled as a voltage source with a peak-to-peak output voltage that is scaled to the voltage that would appear on the divider's output if the capacitor was not present.

The low pass filter is a single pole RC filter. To analyze the circuits performance, a simplified model (below) can be used.

This model of the low pass filters simplifies analysis

A simplifying assumptions in modeling the output filter is to assume that the output resistance of the PWM signal from the microcontroller is negligible. Judging from the AT90S2313 data sheet,. when operating at 5 volts, the out put resistance is around 28 Ohms, so its safe to say its negligible compared to the 160k Ohm resistor in series with it. In the simplified model the equivalent series resistance is equal the the parallel combination of the 160k and 39k resistors and the driving signal source is modeled as a voltage source with a peak-to-peak output voltage that is scaled to the voltage that would appear on the divider's output if the capacitor was not present.

Ripple in the PWM DAC voltage

The PWM circuit drives a 5:1 voltage divider made with a 160K and a 39K resistor, with a .033 uf capacitor across the 39K resistor. If the output resistance of the PWM is assumed to be negligible compared to the 160K resistor, the resistance seen by the .033 uf capacitor is that of the 39k resistor in parallel with the 160k resistor, making the equivalent resistance = 31.36k. The time constant of the circuit is then 31.36k x .033 uf = 1.035 milliseconds.

The worst case for ripple voltage is when the PWM circuit generates a 50% duty cycle. At this time, the average voltage across the capacitor is 50% of the maximum, or 0.5 volt, and the .033 uf capacitor is charged toward 1.0 volt and discharged toward 0 volts through the equivalent resistance of 31.36k.

From formula 1 in the box above, the ripple voltage is 12.17 millivolts. One lsb is 1 volt/64 =15.38 millivolts. The ripple is 12.17/15.38 =0.79 lsb. A larger capacitor will reduce ripple almost as the inverse ratio of the capacitance change.

Initial settling time for the PWM DAC

The above calculation give 4.3 milliseconds for 1 lsb settling time. In the source code listing, 5 milliseconds are used, assuring that the PWM value will settle less than 1 lsb during the course of the waveform capture.

Error in settling for one lsb step

Formula 1 was applied to the question of error in settling time for one lsb step.

Formula 1B:

E0/Ei = 1- exp (-T/t)

For a 1 millisecond settling time which was used in the assembler source code, and a 1.035 millisecond time constant on the filter, step change settles to 61.9% of final value, so the error is 1-0.619 = 0.38 lsb. An easier way would be to say that that the settling time is about one time constant, which would settle to within 62.3% of final value, and that is how the settling time was selected.

Adding an offset control and input buffer

The FET provides an offset allowing the input to swing above and below ground as well as
moving the input to the AT90S2313's on-chip comparator away from ground and enabling

From the AT90S2313 data sheet, the comparator's differential gain looks good enough for 6 bit waveform capture, even around ground, but I'm a lot more comfortable running the comparator around mid-supply where the offset-vs-input voltage curve is nearly flat. Also, moving the scale up to, say 2.5V ± 500 mv gives a chance for offset adjustment in both directions. Level shifting the input signal up above ground also provides the opportunity to digitize signals below ground because this will level shift signals below ground to within the comparator's input range.

A JFET source follower is an ideal way to move the input signal up to a more positive voltage without loosing much in the way of signal level or bandwidth. I used an MPF102 in my own circuit because I have some. Lots of small signal JFETs should work well for this. Pinchoff voltage is the FET parameter that most affects the offset because for most FETs, this parameter varies widely. To obtain the approximate 2.5 volt offset (the DC voltage on the FET source when the gate is grounded), one can hand select an FET, adjust the source resistor (15k in the circuit above) or a combination of the two. The higher the value of the resistor, the higher the offset voltage, up to nearly the pinchoff voltage of the FET (which is usually specified at a very low current). Be aware that the source resistance affects the tradeoff between bandwidth and the signal loss. As the resistor is made larger, the bandwidth will decrease and as the resistor is made smaller, the gain of the source follower drops. For my particular circuit layout and its parasitic capacitance, 15K was about the upper limit for 1 million samples per second.

To accommodate the shift in input signal, it is necessary to shift the DC level of the waveform on the other input of the comparator. One way to add an adjustable DC offset to the output of the PWM circuit without affecting the RC filter's response time is to use and adjustable constant current source. The one shown in the circuit above uses a 2N2907 transistor. Collector current is equal to the Alpha of the transistor times the emitter current. The emitter current is set by the voltage across the 8.2k emitter resistor, and the voltage across the emitter resistor is one diode drop more positive than the voltage on the transistor's base as set by the wiper of the potentiometer. The diode in series with the clockwise leg of the potentiometer compensates for the approximately 1.8 millivolts per degree C change in base-emitter voltage of the 2N2907. Note that at frequencies of interest, the output impedance of the 2N2907 is very high and relevantly constant compared with the RC filter's impedance and so has virtually no effect on the filter performance regardless of the offset voltage, unless the the transistor approaches saturation.