; Flash LEDs on R/C Airplane. ; Initial goal: flash by taking output pin high for 100 ms every 500 ms. ; This program expectes to run on an ATTINY12 with the 1.2 Mhz internal RC clock. ; T12astrobe081028A Released version. ; T12astrobe081027A Initial code. ; ASSIGNMENT OF PORTB I/O PINS ;0 500 ms interval, 100 ms on ;1 500 ms interval, 50 ms on ;2 250 ms interval, 100 ms on ;3 250 ms interval, 50 ms on ;4 10 Hz square wave ;5 Reset pin. ;6 Does not exist on AATTINY12. ;7 Does not exist on AATTINY12. .include "tn12def.inc" .equ reload = $CC ; Timer preload/reload value. $CC. .def temp = r16 ; Scratch. .def sregtemp = r17 ; Place to save status register during interrupts. .def tempi = r18 ; Scratch register for use in timer overflow register. .ORG $0000 rjmp reset reti ; External interrupt handler - not used. reti ; Pin change interrupt -not used. rjmp tovflo ; timer overflow interrupt handler. reset: ldi temp,0b00011111 ; Load data direction value for PORTB. out DDRB,temp ldi temp,0b00000000 ; Start with all outputs low. out PORTB,temp ldi temp,$80 out ACSR,temp ; Turn off comparitor (save a little power).. ldi temp,0b00000101 out TCCR0,temp ; Set timer prescaler to clock/1024 ldi temp,reload ; Preload timer counter. out TCNT0,temp ldi temp,$02 ; Enable timer overflow interrupts. out TIMSK,temp sei ; Enable interrupts in general rjmp main ;///////////////TIMER OVERFLOW SERVICE////////////////// tovflo: in sregtemp,SREG ; Save the status register contents ldi tempi,reload ; Re-preload load counter. out TCNT0,tempi out SREG,sregtemp ; Restore the status register contents reti wait_50ms: ldi temp,$22 ;enable sleep and set T0 to respond to falling edge out MCUCR,temp ;enable sleep mode ldi temp,$40 ;enable external interrupt 0 out GIMSK,temp sei ;assure interrupts are enabled sleep ret .db "Copyrights reserved Dick Cappels www.projects.cappels.org October 28, 2008 Code: T12astrobe081028A" main: sbi PORTB,0 sbi PORTB,1 sbi PORTB,2 sbi PORTB,3 sbi PORTB,4 rcall wait_50ms cbi PORTB,1 cbi PORTB,3 cbi PORTB,4 rcall wait_50ms cbi PORTB,0 cbi PORTB,1 cbi PORTB,2 sbi PORTB,4 rcall wait_50ms cbi PORTB,4 rcall wait_50ms sbi PORTB,4 rcall wait_50ms sbi PORTB,3 sbi PORTB,0 sbi PORTB,2 cbi PORTB,4 rcall wait_50ms cbi PORTB,3 sbi PORTB,4 rcall wait_50ms cbi PORTB,0 cbi PORTB,2 cbi PORTB,4 rcall wait_50ms sbi PORTB,4 rcall wait_50ms cbi PORTB,4 rcall wait_50ms ;rjmp main sbi PORTB,0 sbi PORTB,1 sbi PORTB,4 sbi PORTB,2 sbi PORTB,3 rcall wait_50ms cbi PORTB,1 cbi PORTB,3 cbi PORTB,4 rcall wait_50ms cbi PORTB,0 cbi PORTB,1 cbi PORTB,2 sbi PORTB,4 rcall wait_50ms cbi PORTB,4 rcall wait_50ms sbi PORTB,4 rcall wait_50ms sbi PORTB,0 cbi PORTB,4 sbi PORTB,2 sbi PORTB,3 rcall wait_50ms cbi PORTB,3 sbi PORTB,4 rcall wait_50ms cbi PORTB,0 cbi PORTB,2 cbi PORTB,4 rcall wait_50ms sbi PORTB,4 rcall wait_50ms cbi PORTB,4 rcall wait_50ms rjmp main ;end of assembly souce listing