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EDFET Buffer
Emitter-Driven FET Complimentary Pair Gives Extended Frequency Response and Controlled Bias Current

Photo 1. The EDFET drives like a FET, but with the
bias stability of bipolar. Amps of output current can
be controlled by milliamps of input current. The
current gain is a design choice dictated by

Figure 1. Example application of the EDFET buffer, here is used to drive a dynamic speaker.  The output stage is shown in Photo 1.

Two of things you have to consider when adding a power output stage to an op-amp circuit are the frequency response and the cross-over distortion in that stage. This is especially true with wide band amplifiers, where the unity gain crossover needs to be at several hundred kilohertz. The stage is driven much the same as a complimentary pair output stage, but with the current gain that comes with using FETs., and with feedback within the output stage that that extends the buffer's bandwidth and regulates the quiescent current. More predictable operation allows the designer to design a circuit lower overall power dissipation and better closed loop stability.

The Basic Unity Gain Buffer

Figure 2. In this positive driving section
of the EDFET buffer, inverting stage, Q1
gets offset corrected feedback through
diode connected Q2.

The EDFET complimentary buffer is made up of a pair of unity gain buffers, one that drives in the positive direction and the other that drives in the negative direction. Pictured above is the positive driving half of the output stage. Gain to make the output signal track the input signal comes from inverting transistor, Q1. The input signal is applied to the emitter of Q1 and the output of the amplifier is raised one diode drop to match the forward base-emitter drop of Q1, by diode connected transistor Q2. The buffer's offset is determined by the log of the magnitude of the mismatch in the emitter currents in Q1 and Q2, and it is directly proportional to the absolute temperature. This is seen by the the expression for a diode drop, which is:
(expression for doide voltage) where

Vdiode = the voltage across the base and emitter in volts,
K = Boltzman's constant = 1.38062 E-12 Jouls/degrees Kelvin,
T = temperature in º kelvin,  ºK= ºC + 273.5 ºK.,
q = the unit of electron charge = 1.602 E-19 coulombs,
I =  emitter current, and
I0 = The junction saturation current, usually in the range of 10-14 to 10-15 amps.
Since the saturation current usually isn't published for the transistors this expression is only usefully for appreciating the dependence of junction voltage on current and temperature.  You can come up with your own value of I0 for a given transistor if you know all the other parameters and solve the above formula for I0.  By the way, since, for most practical uses, you will be running at more than a thousand times the saturation current, the "+1" term can be dropped from practical calculations.

When the junctions are biased for zero volts offset, the temperature coefficient of the offset becomes zero (Ideally). For a low distortion class B stage, this is the bias point to shoot for. The starting point is to use equal value resistors for R1 and R2. As the base-emitter voltage of Q2 decreases, the quiescent current (current when not driven) through the output stage will increase.

Inverting Stage Open Loop Gain
The open loop gain of the inverting stage, Q1,  is a key component in determining the bandwidth of the overall buffer.

A formula that calculates the DC open loop gain of a grounded emitter  amplifiers that has served me well for many years assumes that the collector resistance of the circuit is much greater than the intrinsic resistance of the emitter circuit, and that there are no significant loads on the collector, which is something that suites Q1 in this buffer, since it is intended to be driven by a low impedance source in the form of an op-amp and the gate of Q3 does not present a significant DC load.
, where
Vr = the voltage across the collector resistor in volts,
q = the unit of electron charge = 1.602 E-19 coulombs
K = Boltzman's constant = 1.38062 E-12 Jouls/degrees Kelvin, and
T = temperature in º kelvin,  ºK= ºC + 273.5 ºK.
A further simplification can be made, if one assumes room temperature operation. At room temperature q/KT = 38.5, making the open loop gain at DC equal to about 38 X VR. I've used this approximation for many years and it has served me well.

Frequency Response
The inverting stage's open-loop gain corner frequency, Fc, is that frequency beyond which, open loop gain is cut in half each time the frequency is doubled (-6 db/octive). The buffer will maintain unity gain until about the frequency at which the open loop gain reaches unity (fi,  0 dbintercept frequency). At frequencies above that, the buffer's  gain will roll off at 66 db/octive As pictured in the plot below, the buffer's unity gain crossover frequency can be extended two or more octaves, provided there is sufficient voltage across the collector resistor to obtain sufficient gain. For this reason, in some circuits, it will pay to connect R1 and R2 to a significantly higher power supply voltage than the drain of the FET, to achieve high bandwidth with reasonable power dissipation (see the schematic at the end of this page).

Figure 3. Frequency response of the transistor (inverter)
part of the stage and the overall response of the buffer.

Because the FET's high input capacitance is large and dominates the gate node, Q1's capacitance is acknowledged but cheerfully ignored. It is the FET's input capacitance and Q1's collector resistance that is used to calculate the corner frequency of the open loop gain function.

Fc = 1/( 2 Pi R1 Ciss).

This formula is can be combined with the formula for gain, described above, to give us the value necessary for R1 to as a function of the FET characteristics, output condition, and desired unity gain bandwidth at room temperature.

R1 = the value of R1 in ohms,
VA = the power supply voltage applied to R, referenced to ground,
VGmax = The maximum gate voltage needed to drive the maximum output                     voltage relative to ground, Find this using the FET data sheet.
Ciss = FET input capacitance at the maximum output voltage, and
Fi = the desired 0 db intercept frequency (unity gain bandwidth of the buffer). 

As an example, for the audio amplifier using a EDFET buffer shown in Figure 1. The following assumptions are applied: The maximum output voltage is 5 VDC with respect to ground, the power supply (VA) is 12 VDC, the maximum gate voltage is 8 VDC, the input capacitance, Ciss of the BUZ73 is 500 pf, and an intercept of 2 MHz is desired so as to have plenty of phase margin (for the largest frequency difference between the point the closed loop response of the  amplifier reaches 00 dband the point that the FET buffer starts to roll off). The formula suggest that R1 should be less than 24K. I used 20k resistors, which I had on hand and should give even a little more mmargin and the circuit seems to work fine (indeed, I am listening to MP3s from my iPod on this amplifier driving a speaker as I write this).

Figure 4. This is the gain plot for
the audio amplifier at the top of the page.

It was necessary to roll off the closed loop gain of the circuit because the if I hadn't there would have been insufficient phase margin between the buffer's rolloff frequency and the closed loop gain of the LM324 (the intercept would have been at about 2 MHz).

Notice that the buffer used for the audio amplifier could have been rolled off at 200 kHz instead of 20 kHz and adequate phase margin maintained. When selecting R1, remember that the worst case frequency response and therefore phase margin, occurs when the output signal is closes to the power supply voltage because the buffer's open loop response is the lowest and the FET's input capacitance is the highest.

In practice, the open loop corner frequency will be somewhat lower, hence the buffer unity gain crossover will also be lower, so while the formula will give a good starting point for a prototype, expect to decrease the resistors a bit if the crossover frequency is critical (such as for preventing the op-amp from oscillating).  

Making It Class B

Figure 5. Classic bipolar complimentary pair.

Start by taking a look at the classic bipolar complimentary emitter follower. It is merely two buffers - one positive-driving, and one negative-driving, connected to together, with resistors in series with the outputs to limit the quiescent emitter current. In this circuit, the current through the bias diodes is increased to increase the voltage drop across the emitter, resistors, thus establishing the bias current. The more current through the diodes, the higher the quiescent current, and the lower the crossover distortion. In the case of the EDEFT buffer, the output transistors are the FET's increasing the current and the diodes are the input transistors.

Setting Quiescent Source Current
Figure 6. This particular EDFET buffer is from a CRT deflection amplifier.
The FET drains are connected to lower voltage power supplies to minimize
power dissipation. Load current was over 6 amps peak-to-peak. This application
is particularly sensitive to noise and crossover distortion, and the EDFET
performed superbly.
The bias current is set in a manner similar to the classic complimentary pair. I am only using one source resistor to set the bias current. In some high frequency applications in which a capacitive load is being driven (for example, a 50 video amplifier) the waveform symmetry would be preserved by splitting the resistor and taking the output signal at the tap as shown in the classic complimentary pair, but for applications one is likely to be using power MOSFETs for, it is unlikely that a second resistor would do more than fulfill an emotional need to make the circuit look symmetric.

The quiescent point source current is equal to the sum of the offsets in the postive-driving and negative-driving parts of the stages divided by the source resistor. The way I set the quiescent bias is to first select the collector resistors (R1 in the schematic of the single ended buffer), and then pick the bias resistors. In the circuit above, using 1 k resistors to bias the diode connected transistors and 2 k resistors for the collector loads on the inverting stage (as shown) the output stage is just barely into conduction, drawing a few hundred mircoamps. This is near the zero bias point at which the bias current should vary little with temperature. Increasing the 1k resistors (R2) would increase the quiescent current.
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First posted in January, 2005; minor corrections October 2010.

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